1. Field of the Invention
The present invention relates to electronic circuits, and more particularly to differential signal generators.
2. Description of Related Art
Differential signal generators are used to generate a true/complement output signal pair in response to a single-ended input signal. A differential signal generator receives a single-ended input signal that transitions between a high value (logical "1") and a low value (logical "0"), and generates an output signal pair that includes a first signal and a second signal. For instance, the first signal can be the true signal with the same logical value as the input signal, and the second signal can be the complement signal with an opposite logical value to the input signal. Alternatively, the first signal can be the complement signal and the second signal can be the true signal.
Differential signal generators are used in a variety of applications. For instance, a differential signal generator can be used to drive the switches of a charge pump in a phase-locked loop. In this application, it may be necessary for the output signal pair to be level shifted with respect to the input signal, such that the output signal pair has a greater voltage swing than the input signal. Furthermore, it may be critical for the output signal pair to cross each other at about the 50% cross-point (between their high and low logical values) in response to transitions of the input signal in order to assure proper operation of the charge pump.
FIG. 1 is a schematic diagram of a conventional differential signal generator 10 which provides a level-shifted output signal pair which cross each other at about the 50% cross-point, and FIG. 2 is a timing diagram of signals associated with differential signal generator 10. Differential signal generator 10 receives single-ended input signal V12 at input terminal 12, and generates a true/complement intermediate signal pair consisting of signal V14 (the true signal) at node 14 and signal V16 (the complement signal) at node 16. Input signal V12 is a digital signal that transitions between a high value (or logical "1" at supply voltage Vdd1) and a low value (or logical "0" at ground), and intermediate signal pair V14 and V16 are digital signals that transition between a high value (or logical "1" at supply voltage Vdd2) and a low value (or logical "0" at ground). Supply voltage Vdd2 is greater than supply voltage Vdd1. For example, supply voltage Vdd1 is in the range of 1.2 to 2.5 volts, and supply voltage Vdd2 is in the range of 3.0 to 3.6 volts. As a result, intermediate signal pair V14 and V16 is level shifted with respect to input signal V12. For illustration purposes, the signals have rise and fall times of about 100 picoseconds.
Differential signal generator 10 includes inverting stage 20, N-channel transistors 22 and 24, and P-channel transistors 26 and 28. Transistors 22 and 24 are about twice the size of and have larger drive currents than transistors 26 and 28. Therefore, when transistors 22 and 26 are turned on, node 14 is pulled essentially to ground, and when transistors 24 and 28 are turned on, node 16 is pulled essentially to ground.
When input signal V12 is high, transistor 24 turns on and transistor 22 turns off. This pulls node 16 essentially to ground, thereby turning on transistor 26, which in turn pulls node 14 to voltage Vdd2 and turns off transistor 28. Accordingly, signal V14 goes high and signal V16 goes low in response to input signal V12 going high. Conversely, when input signal V12 is low, transistor 24 turns off and transistor 22 turns on. This pulls node 14 essentially to ground, thereby turning on transistor 28, which in turn pulls node 16 to voltage Vdd2 and turns off transistor 26. Accordingly, signal V14 goes low and signal V16 goes high in response to input signal V12 going low. Advantageously, cross-coupling transistors 26 and 28 avoids a crowbar current path from Vdd2 to ground.
Unfortunately, however, as seen in FIG. 2, when transitions occur, intermediate signal pair V14 and V16 do not cross each other at or near the 50% cross-point. For instance, when input signal V12 transitions low, transistor 24 turns off without having an appreciable effect on node 16 since node 16 is at ground and transistor 28 is off After input signal V12 propagates through inverting stage 20, transistor 22 turns on and pulls node 14 towards ground. Thereafter, transistor 28 turns on and pulls node 16 towards voltage Vdd2, and transistor 26 turns off. Thus, the falling edge of signal V14 leads the rising edge of signal V16 by time T1 (about 80 to 120 picoseconds) associated with the turn-on time of transistor 28, and signals V14 and V16 cross each other near ground. Similarly, when input signal V12 transitions high, transistor 24 turns on and pulls node 16 towards ground. Thereafter, transistor 26 turns on, and input signal V12 propagates through inverting stage 20 so that transistor 22 turns off, node 14 is pulled towards voltage Vdd2, and transistor 28 turns off Thus, the falling edge of signal V16 leads the rising edge of signal V14 by time T2 (about 80 to 120 picoseconds) associated with the propagation delay of inverting stage 20, and signals V14 and V16 cross each other near ground. Consequently, intermediate signal pair V14 and V16 is a "make or break" signal pair without a 50% cross-point.
Differential signal generator 10 addresses this problem by coupling inverter chains 30 and 32 to nodes 14 and 16, respectively, to generate true/complement output signal pair V34 and V36 at output terminals 34 and 36, respectively. Inverter chains 30 and 32 are each composed of successive inverting stages. As seen in FIG. 2, inverter chains 30 and 32 introduce suitable delays so that output signal pair V34 and V36 cross each other at about the 50% cross-point. This can be accomplished, for instance, by designing appropriate beta ratios and/or loading for the inverting stages.
A major drawback of differential signal generator 10 is that inverter chains 30 and 32 occupy a considerable amount of surface area. It is, of course, highly desirable to reduce the size of a given circuit whenever possible. Another drawback of differential signal generator 10 is that the delays introduced by inverter strings 30 and 32 are highly sensitive to process variations (effective channel lengths, gate oxide thicknesses, etc.).
Accordingly, a need exists for a differential signal generator that provides a true/complement output signal pair that cross each other at a predetermined cross-point, such as the 50% cross-point, in response to a single-ended input signal, particularly where the signal generator reduces space requirements and provides level shifting.